This invention relates generally to semiconductor memory cells, and more particularly to dynamic semiconductor memory cells provided with automatic refreshing.
In the semiconductor memory industry, dynamic memory cells which require only one transistor and one capacitor are widely used, and fully static memory cells which require only four transistors and two resistors are widely used. Other types of static memory cells use six transistors. Typically, in a dynamic memory cell without automatic refreshing, the datum stored in the cell is periodically refreshed by first reading the datum and then re-entering it. The number of memory cells that can be simultaneously refreshed is limited to the number of sense amps provided. Also, additional circuitry is required to control the refresh operation, and the memory is not available for read or write operations while it is being refreshed. Static memory cells do not require refreshing, but such cells are usually more complex and space consuming than dynamic memory cells. A dynamic memory cell with automatic refreshing capability is one which has a refresh operation that does not require that the stored datum be read. Therefore, other factors being equal, the time interval required to refresh a memory cell with automatic refresh capability is less than that required to refresh a cell without automatic refresh capability. Also, in an array of dynamic memory cells with automatic refresh capability, the number of cells that can be simultaneously refreshed is not limited to the number of sense amps provided.
In the prior art, memory cells with automatic refreshing have been developed, but suffered from various limitations. For example, the four transistor plus charge pumps memory cell requires an area comparable to some static cells and provides only modest power advantages over some static cells. An Automatic Refresh Dynamic Memory was described by H. J. Boll et al, at the International Solid State Circuits Conference held in Feb. 1976, and K Shiga et al described A Monostable CMOS RAM with Self-Refresh Mode at the same meeting and subsequently published a description of the cell in the IEEE Journal of Solid State Circuits, Vol. SC-11, No. 5, Oct. 1976, p. 609. Both of these more recent memory cells required four transistors, and the later required complementary IGFETs. Moreover, in both of the last two automatic refreshing memory cells, the read operation is destructive, so that in an array of such cells, multiple sense amps must be provided.